CMOS developmenet for the readout of Germanium Strip Detectors

Germanium strip detectors (GSDs) require very low noise electronics and a large number of channels. A typical detector will have on the order of 50-200 channels, depending on the size and application. We have undertaken an ASIC development program with Oak Ridge National Laboratory and a cooperative agreement with Physical Sciences Inc. to develop chips for GSDs. Our chip set includes a low power preamplifier, shaping amplifier, and a peak detect and hold circuit. The entire analog chain requires ~3 mW power per channel, has a 9 microsecond peaking time, and a noise performance ~300 e rms when operated with a typical detector. Translated into detector performance, our Ge strip detector should achieve 2.1 keV FWHM energy resolution with this chip.

A simple test configuration of the prototype electronics is shown below. Individual ASICs are outlined in the blue boxes with their functional components shown within.

At the prototype stage, each of the functional blocks has been developed as a separate chip to reduce development risk. The chips are controlled and readout using a data acquisition card in a PC. This system is realized in the test board picutred below.

The develoment chip set is divided into two parts. The upper row of four chips are preamp/shaper chips. The lower row are peak-detect, track-and-hold chips. Each chip has two channels, thus the test board is an eight channel system.

Noise slope measurements

We have obtained excellent low noise performance from the preamplifier/shaping amplifier chip. Noise obtained from a preamplifier is a function of the capacitance of the detector, as shown in this Figure. Two types of chips were fabricated and tested using a PMOS and an NMOS process respectively. Our NMOS chip has a particularly low noise slope, thus it performs well for detectors with capacitance ~5-30 pF (typical of a germanium strip detector) to large area silicon detectors with capacitance ~100 pF.

The prototype chip set has demonstrated excellent linearity over a wide range of output voltage. These CMOS chips operate off a single 5V supply. The output can swing to within 0.5 V of the supply or ground and still maintain good linearity.

The next phase of this development is to integrate an entire 16 channel system (essentially the function of two of the test boards pictured above), all onto a single chip. The new chip will add features of adjustable gain and shaping time, thus making it useful in a wider range of applications and the commercial market.

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Performance results of our prototype chips are found in our preprints list.

For questions, please contact Richard Kroeger.

last updated: 29-Oct-1998